4.6 Article

Threshold Voltage Model for 2-D FETs With Undoped Body and Gated Source

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 70, Issue 5, Pages 2575-2580

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2023.3255833

Keywords

Logic gates; Films; Tunneling; Two dimensional displays; Threshold voltage; Metals; Junctions; Field-effect transistor (FET); gated source; surface potential; threshold voltage model; two-dimensional (2-D) materials

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In this article, a threshold voltage model for 2-D materials-based FETs is derived using an analytical solution to Poisson's equation at the source region. The effect of fringing fields on the underlapped region is studied and incorporated using conformal mapping. The model highlights the dependence of the turn-on condition on various factors, including the barrier height, device geometry, and gate-to-source overlap length. It is verified with numerical simulations and experimental data.
In this article, a threshold voltage model for two-dimensional (2-D) materials-based field-effect transistors (FETs) with an undoped body and a gated source is derived based on an analytical solution to Poisson's equation at the source region. The effect of fringing fields on the underlapped region for the case when the gate has almost no overlap with the source is also studied and incorporated using conformal mapping. The derived threshold voltage model highlights the dependence of the turn-on condition on the barrier height at the metal/2-D interface, the geometry of the device, particularly on the 2-D film and oxide thickness, and the gate-to-source overlap length. Modifications on the barrier height at the metal/2-D junction due to the widely observed metal Fermi level pinning (FLP) effect on fabricated devices are also integrated. The proposed new model is verified by numerical simulations and published experimental data with close agreement.

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