Journal
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume 42, Issue 6, Pages 2030-2042Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCAD.2022.3209530
Keywords
Artificial circuit; data preparation; machine learning (ML); place-and-route (P&R) benchmark; routability prediction
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Design optimization methods using machine learning have been studied to reduce the number of design iterations in physical design flow. The lack of place-and-route benchmarks is a major problem for ML research. We introduce a framework to construct realistic P&R benchmarks for training ML applications. Our approach improves the model's ability to predict the routability of unseen real circuits, achieving significant improvement in F1 score for timing and routing failure prediction.
Many design optimization methods using machine learning (ML) techniques have been investigated to reduce the number of design iterations in the physical design flow. The demand for big data to support ML research has been increasing, but the lack of place-and-route (P&R) benchmarks is one of the major problems. We propose a framework to construct realistic P&R benchmarks for use in training ML applications. The framework can organize the P&R database using an artificial netlist generator, which can create any gate-level netlist from user-specified input parameters that represent the topological characteristics of the circuit. We show that a training dataset that contains many artificial gate-level netlists can improve the generalizability of the model to predict the routability for unseen real circuits without using expensive real-world data. Compared to the model that had been trained with real-world circuits, we improved the F1 score in predicting the timing and routing failure by 26.4% and 54.5%, respectively.
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