MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM

Conventional computing architectures based on the von Neumann structure are suffering from the severe 'memory wall' issue due to the isolation and speed mismatch between memory and processor. As a promising solution, the concept of logic in-memory (LiM) has been proposed to effectively reduce the overhead of data migration and has been extensively studied in various memory technologies such as SRAM, DRAM, MRAM, ReRAM, etc. Among them, SOT-MRAM combines the advantages of non-volatility, low static power consumption, ultra-fast read/write speed, and high density, has emerged as one of the most promising candidates for low-power LiM implementations. In this paper, four in-memory logic operations, AND, OR, MAJ and full-addition (FA), are proposed based on the Unipolar Switching (US) SOT-MRAM devices. Incorporating the emerging switching behavior of SOT-MRAM, these operations can be performed with the basic memory access operations (read/write) with negligible modifying peripheral circuits. Meanwhile, by optimizing the operation steps, the performance degradation caused by the instability of SOT-MRAM device can be minimized in the proposed LiM architecture. Detailed simulation results show that the proposed design can reduce the latency (energy) of AND, OR operations at least by 71.2%, 74.4% (30.0%, 35.4%) compared with the existing SRAM and STT-MRAM designs. For MAJ and FA operations, the performance is improved by at least 34.7% and 44.8% compared to the existing design. The robustness of our design is demonstrated by the 100% pass of the 1000 samples Monte Carlo simulations for the sufficient switching current margin and the effectiveness of basic operations.

Automated summary

Conventional computing architectures based on the von Neumann structure are facing the problem of the 'memory wall' due to the mismatch between memory and processor. The concept of logic in-memory (LiM) is proposed as a solution to reduce data migration overhead, and it has been extensively studied in various memory technologies. Among them, SOT-MRAM stands out as a promising candidate due to its advantages of non-volatility, low power consumption, high speed, and high density. This paper proposes in-memory logic operations based on US SOT-MRAM devices, which can be performed with minimal modifications to peripheral circuits and optimized to minimize performance degradation caused by device instability.