Journal
IEEE ELECTRON DEVICE LETTERS
Volume 44, Issue 6, Pages 883-886Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2023.3268179
Keywords
Antiferroelectric; ferroelectric; grain size; grain boundary; atomic layer deposition temperature; HfZrO
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We fabricated FeRAM and FeFET devices using a bilayer HfxZr1-xO2 (HZO), consisting of 5-nm-thick antiferroelectric HZO and 5-nm-thick ferroelectric HZO. Grazing-incidence x-ray diffraction and TEM results showed higher orthorhombic phase and larger grain size. By employing low temperature atomic layer deposition, we improved the leakage current (<3 x 10(-5) A/cm(2) under +/- 2V), gate control ability, memory window (>1.5V) and endurance (>10(7) cycles), indicating the promising potential of low-temperature ALD for non-volatile memory devices.
We fabricated FeRAM and FeFET with a bilayer HfxZr1-xO2 (HZO), which comprises 5-nm-thick antiferroelectric HZO and 5-nm-thick ferroelectric HZO. Higher orthorhombic phase and large grain size were shown in grazing-incidence x-ray diffraction and TEM results, respectively. By using low ALD temperature, the leakage current (<3 x 10(-5) A/cm(2) under +/- 2V), gate control ability, the memory window (>1.5V) and the endurance (>10(7) cycles) have been improved. These results suggest that a low atomic layer deposition temperature is a promising process for use in non-volatile memory devices.
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