Design of CNTFET-Based Ternary and Quaternary Magnitude Comparator

This paper presents a novel power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based design of a quaternary magnitude comparator for single and double digits. It also proposes an improved circuit of the ternary single-digit comparator and a novel design of the double-digit ternary comparator. The designs make use of the pass transistor logic and transmission gates, resulting in a more power and energy-efficient design with a lower number of CNTFETs when compared with existing designs. Besides, this paper also proposes a generalized circuit of magnitude comparator for multiple digits. The proposed circuits are simulated in HSPICE using the 32 nm CNTFET model presented by Stanford University. Average power and propagation delays are observed and the power-delay-product (PDP) is calculated in each case. The impact of process parameter variations has been analyzed through Monte Carlo simulation and has been presented in the form of two-dimensional graphs.

Automated summary

This paper presents a novel design of a power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based quaternary magnitude comparator for single and double digits. The study also proposes an improved circuit for a ternary single-digit comparator and a new design for a double-digit ternary comparator. By utilizing pass transistor logic and transmission gates, the designs achieve higher power and energy efficiency with a reduced number of CNTFETs compared to existing designs. Additionally, a generalized circuit for a magnitude comparator of multiple digits is proposed. The proposed circuits are simulated and analyzed for average power, propagation delays, and power-delay-product (PDP) using the 32 nm CNTFET model provided by Stanford University. The impact of process parameter variations is also investigated through Monte Carlo simulation.