A 1.25-1.8 V reference-free capacitor sample-hold oscillator architecture with 22.19 ppm/°C at 58.9 kHz

This paper presents a capacitor sample-hold oscillator architecture which realizes temperature-stabilized operation without a precise reference generator by using a capacitor to sample-hold the peak charge voltage of the previous phase as the reference for the current phase. Due to its dual-way charging and discharging structure, the peak charge voltage for each phase will eventually stabilized around half the supply voltage. The frequency of the oscillator depends on the RC time constants of capacitors charging (discharging) across passivelytemperature-stabilized resistive elements and the comparator delay time. By analyzing the temperature characteristics of the comparator delay time and using temperature compensated bias currents to achieve temperature stabilization of the delay time, this architecture improves the overall temperature stability. This architecture has been designed and verified in 0.18-mu m CMOS technology. The simulation results demonstrate this design consumes 7.99 mu W from a 1.8 V supply voltage at 58.9 kHz and achieves a temperature stability of best 22.19 ppm/celcius(TT Corner) from - 40 degrees C to 90 degrees C, and frequency variations of +/- 0.3 % for supply changes from 1.25 to 1.8 V.

Automated summary

This paper introduces a capacitor sample-hold oscillator architecture that achieves temperature-stabilized operation without a precise reference generator by using a capacitor to sample-hold the peak charge voltage of the previous phase as the reference for the current phase. The frequency of the oscillator depends on the RC time constants of capacitors charging or discharging and the comparator delay time. The architecture improves temperature stability by analyzing the temperature characteristics of the comparator delay time and using temperature compensated bias currents.