Journal
ELECTRONICS
Volume 12, Issue 2, Pages -Publisher
MDPI
DOI: 10.3390/electronics12020367
Keywords
QCA cell; memory cell; QCADesigner; low power dissipation; cost-efficient
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In this paper, a cost-efficient single layer SRAM cell design in Quantum-dot Cellular Automata (QCA) is proposed. It achieves an overall improvement in cell count, area, latency, and QCA cost compared to the reported designs. This design can be used to construct higher-order nanoscale memory structures.
SRAM or Static Random-Access Memory is the most vital memory technology. SRAM is fast and robust but faces design challenges in nanoscale CMOS such as high leakage, power consumption, and reliability. Quantum-dot Cellular Automata (QCA) is the alternative technology that can be used to address the challenges of conventional SRAM. In this paper, a cost-efficient single layer SRAM cell has been proposed in QCA. The design has 39 cells with a latency of 1.5 clock cycles and achieves an overall improvement in cell count, area, latency, and QCA cost compared to the reported designs. It can therefore be used to design nanoscale memory structures of higher order.
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