A Gain-Enhanced Low Hardware Complexity Charge-Domain Read-Out Integrated Circuit Using a Sampled Charge Redistribution Technique

A gain-enhanced low hardware complexity charge-domain read-out integrated circuit is implemented. By adopting a sampled charge redistribution technique, low hardware complexity is achieved, which in turn saves 10% of the die area and provides 33% gain enhancement compared to the conventional topology. In particular, a charge-domain discrete-time filter with inherent reconfigurability is a key building block, which can also act as an anti-aliasing filter before the analog-to-digital converter. The measurement results show good agreement with the intended frequency response. The proposed filter is implemented using a 0.11 mu m CMOS process and occupies 0.15 mm(2).

Automated summary

This article presents a gain-enhanced, low hardware complexity charge-domain read-out integrated circuit, achieved through sampled charge redistribution technique, saving die area and providing gain enhancement. The charge-domain discrete-time filter with inherent reconfigurability works effectively as an anti-aliasing filter.