4.6 Article

A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer

Journal

APPLIED SCIENCES-BASEL
Volume 12, Issue 22, Pages -

Publisher

MDPI
DOI: 10.3390/app122211651

Keywords

coarse-fine input buffer; pre-charge buffer; low-noise amplifier; delta-sigma modulator; incremental delta-sigma modulator

Funding

  1. Ministry of Health and Welfare (MOHW, Korea)
  2. Korea Health Industry Development Institute (KHIDI, Korea)
  3. Practical Technology Development Medical Microrobot Program (R&D Center for Practical Medical Microrobot Platform) [HI19C0642]
  4. Ministry of Science and ICT (MSIT), Korea, under the Information Technology Research Center (ITRC) support program [IITP-2021-2017-0-01635]
  5. Nanomedical Devices Development Project of NNFC

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This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS, achieving high performance as demonstrated by experimental results.
Featured Application Low noise circuit, delta-sigma modulator, analog to digital converter. This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator's architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-mu m CMOS process with an active area of 1.06 mm(2). The total current consumption with the coarse-fine buffer was 1.374 mA.

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