Journal
APPLIED SCIENCES-BASEL
Volume 12, Issue 23, Pages -Publisher
MDPI
DOI: 10.3390/app122312225
Keywords
FPGA; performance; simulation; out-of-order
Categories
Funding
- National Natural Science Foundation of China
- Natural Science Foundation of Hunan Province of China
- [62272475]
- [61872374]
- [61672526]
- [62172430]
- [2022JJ10064]
- [2021JJ10052]
Ask authors/readers for more resources
This paper introduces an effective method, FPGA-enhanced design flow, to address the optimization challenges in modern processor design. By reconsidering FPGA simulation as a performance simulation method, the proposed method improves the accuracy and efficiency of performance simulation for out-of-order processors.
Late-stage (post-RTL implementation) optimization is important in achieving target performance for realistic processor design. However, several challenges remain for modern out-of-order ILP (instruction-level-parallelism) processors, such as simulation speed, flexibility, and complexity problems. This paper restudy FPGA simulation as an effective performance simulation method and proposes FPGA-enhanced design flow as an effective method to address these problems. It features a late-stage aware RTL design that parameterizes various potential design options induced from early-stage optimization. This flow enables the feasibility of late-stage design space exploration. To resolve the performance accuracy of the FPGA system for peripheral designs, reference models are introduced. With an example implementation of out-of-order core running up to 80 MHz, the experimental results show that the proposed method is practical and allows the fine-grain optimization of the processor core to be more effective.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available