Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications

This paper introduces a flexible convolver capable of adapting to the different convolution layer configurations of state-of-the-art Convolution Neural Networks (CNNs). The use of two proposed programmable components achieves this adaptability. A Programmable Line Buffer (PLB) based on Programmable Shift Registers (PSRs) allows the generation of the required convolution masks required for each processed CNN layer. The convolution layer computing is performed through a proposed programmable systolic array configured according to the target device resources. In order to maximize the device resource usage and to achieve a shortened processing time, the filter, data, and loop parallelisms are leveraged. These characteristics allow the described architecture to be scalable and implemented on any FPGA device targeting different applications. The convolver description was written in VHDL using the Intel Cyclone V 5CSXFC6D6F31C6N device as a reference. The experimental results show that the proposed computing method allows the processing of any CNN without requiring special adaptation for a specific application since the standard convolution algorithm is used. The proposed flexible convolver achieves competitive performance compared with those reported in related works.

Automated summary

This paper presents a flexible convolver that can adapt to different convolution layer configurations of state-of-the-art CNNs. The adaptability is achieved by using two proposed programmable components. A Programmable Line Buffer based on Programmable Shift Registers generates the required convolution masks for each processed CNN layer. The convolution layer computing is performed through a proposed programmable systolic array. The experimental results show that the proposed computing method allows for the processing of any CNN without requiring special adaptation for a specific application.