Journal
MICROMACHINES
Volume 13, Issue 12, Pages -Publisher
MDPI
DOI: 10.3390/mi13122110
Keywords
analog-to-digital converter (ADC); energy-efficient; successive approximation register (SAR)
Categories
Funding
- National Natural Science Foundation of China [60976026]
- Key Field Project of Colleges and Universities in Guangdong Province [2021ZDZX1081]
- Key Project of Social Welfare and Basic Research Project in Zhongshan City [2021B2020]
- Construction Project of Professional Quality Engineering [YLZY202001, JD202101]
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This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator, and automatic ON/OFF SAR logic for biomedical applications. The proposed switching scheme reduces the energy consumption significantly and decreases the dependency on accuracy and complexity.
This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient switching scheme achieves an average digital-to-analog converter switching energy of 63.56 CVref2, achieving a reduction of 95.34% compared with the conventional capacitor switching scheme for CDACs. With the switching scheme, the ADC can lower the dependency on the accuracy of V-cm and complexity of DAC control logic and DAC driver circuit. Moreover, dynamic circuits and automatic ON/OFF technology are used to reduce power consumption of comparator and SAR logic. The prototype is designed and fabricated in a 180 nm CMOS with a core size of 500 mu m x 300 mu m (0.15 mm(2)). It consumes 7.6 nW at 1 kS/s sampling rate and 1.8-V supply with an achieved signal-to-noise-and distortion ratio of 45.90 dB and a resulting figure of merit of 51.7 fJ/conv.-step.
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