Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks

Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex NN models remains challenging because different tasks, such as feature extraction and classification, should be performed at different memory elements and arrays. This further increases the required number of memory arrays and chip size. Here, we propose a three-dimensional ferroelectric NAND (3D FeNAND) array for the area-efficient hardware implementation of NNs. Vector-matrix multiplication is successfully demonstrated using the integrated 3D FeNAND arrays, and excellent pattern classification is achieved. By allocating each array of vertical layers in 3D FeNAND as the hidden layer of NN, each layer can be used to perform different tasks, and the classification of color-mixed patterns is achieved. This work provides a practical strategy to realize highperformance and highly efficient NN systems by stacking computation components vertically.

Automated summary

Hardware-based neural networks (NNs) have the potential to revolutionize AI applications by extracting features from unstructured data and learning from them. However, implementing complex NN models is challenging because different tasks require different memory elements and arrays, resulting in increased chip size.