Three-dimensional transistors and integration based on low-dimensional materials for the post-Moore's law era

Since the 1960s, the feature size of metal oxide semiconductor field-effect transistors has been scaled down to sub-micrometer and even nanometer to increase the transistor density on a chip according to the Moore's law, leading to smaller device, faster speed and lower power consumption. In this process, various new materials and technologies have been introduced including SiGe strained silicon and high -k metal gate. Today, tremendous efforts are being made for the use of three-dimensional (3D) technologies such as fin-structured field-effect transistors, gate-all-around field-effect transistors and 3D integration. At the same time, low-dimensional materials such as carbon nanotubes, graphene and transition metal dichalcogenides are being extensively studied for nano-device fabrication. Here, the development of devices using both 3D structures and low-dimensional materials is reviewed. By combining these two key strategies, 3D transistors and integration based on low-dimensional materials are expected to achieve the highest gate control ability and device density, which is promising to continue the Moore's law even further.

Automated summary

Since the 1960s, the size of metal oxide semiconductor field-effect transistors has been scaled down to increase transistor density on a chip. New materials and technologies have been introduced, including SiGe strained silicon and high-k metal gate. The development of devices using 3D structures and low-dimensional materials is reviewed, as they are expected to continue the Moore's law further.