Design of an analog monolithic pixel sensor prototype in TPSCo 65 nm CMOS imaging technology

A series of monolithic active pixel sensor prototypes (APTS chips) were manufac-tured in the TPSCo 65 nm CMOS imaging process in the framework of the CERN-EP R & D on monolithic sensors and the ALICE ITS3 upgrade project. Each APTS chip contains a 4 x 4 pixel matrix with fast analog outputs buffered to individual pads. To explore the process and sensor characteristics, various pixel pitches (10 mu m-25 mu m), geometries and reverse biasing schemes were included. Prototypes are fully functional with detailed sensor characterization ongoing. The design will be presented with some experimental results also correlating to some transistor measurements.

Automated summary

A series of APTS chips, which are monolithic active pixel sensor prototypes, have been manufactured in the TPSCo 65 nm CMOS imaging process for the purpose of CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade project. Each APTS chip consists of a 4 x 4 pixel matrix with fast analog outputs buffered to individual pads. Various pixel pitches, geometries, and reverse biasing schemes have been included to explore the process and sensor characteristics. The prototypes are fully functional and detailed sensor characterization is ongoing, with the design being presented along with experimental and transistor measurement results.