Temperature rise effects on static characteristics of complementary FETs with Si and Ge nanosheets

We simulate the static behavior of Ge-p/Si-n nanosheet complementary FETs (CFETs), where p-type FETs containing Ge nanosheet channels are stacked on top of n-type FETs containing Si nanosheet channels, and we investigate its relation to temperature while comparing it with that of Si-p/Si-n nanosheet CFETs, whose p-type FETs contain Si nanosheet channels. It is found that temperature rise has similar effects on the static characteristics of the two CFETs operating as inverters, although the variations in threshold voltage and noise margin with rising temperature are slightly smaller in the Ge-p/Si-n CFET inverter than in the Si-p/Si-n CFET inverter. The temperature rise effects are fully explained by the temperature dependence of material and carrier properties of Ge and Si.

Automated summary

This study investigates the static behavior of Ge-p/Si-n nanosheet CFETs and compares it with Si-p/Si-n nanosheet CFETs under temperature variations. It is found that the temperature rise has similar effects on the static characteristics of both CFETs operating as inverters, with slightly smaller variations in threshold voltage and noise margin for the Ge-p/Si-n CFET inverter compared to the Si-p/Si-n CFET inverter. The temperature rise effects are fully explained by the temperature dependence of material and carrier properties of Ge and Si.