On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies

In several instances, the electronic appliances used in the Internet-on-Things (IoT) systems fail to perform according to their full capability. One of the main reasons pertaining to this issue is the IoT devices are usually controlled by clock-driven application-specific processors enabling them to communicate over the common network and accomplish given tasks. But these processor chips are mostly prone to supply noise and adversely affect the performance of the IoT systems. In this article, the problem of on-chip power supply noise (PSN) is discussed and how clock gating (CG) is a potential candidate to mitigate i(t) and di(t)/dt which are the dominant factors of instigating the overall on-chip PSN. Majority of the CG schemes are examined and it is seen that LCT-CG implementation can potentially commit 84.44% less PSN compared to the non-gated peer as well as 55.21%, 54.45% and 74.47% lesser than the other CG schemes like LB-CG, (NCMOS)-M-2-CG and DG-CG, respectively. In addition, it is also observed that with the inclusion of LCT-CG in IBM (R) i650 A-Z80 processor chip, the system lifetime is improved by 17.70% compared to the non-gated peer. In addition, the industry standard of implementing CG schemes in integrated circuit (IC) chips is reviewed and it is found quite different from the traditional methods. Therefore, an extensive study is performed to portray the possibility of LCT-CG can become an industry standard in the forthcoming days.

Automated summary

This article discusses the issue of on-chip power supply noise in IoT systems and proposes clock gating as a potential method to mitigate it. The research findings show that the LCT-CG implementation can significantly reduce power supply noise compared to other schemes and improve system lifetime. Additionally, the article reviews the industry standard for implementing CG schemes in integrated circuit chips.