Integrated DC-DC converter design methodology for design cycle speed up

A novel design methodology, enabling extreme design cycle time speed up of DC -DC power converters, is developed. The concept is based on providing high accuracy post-layout RC parasitics aware results, by replacing complicated large RC netlists with small signal approximation models. Scattering parameters analysis is adopted for on the fly performance simulation of the power MOSFET switches' routings, which act as large passive linear networks. The RC parasitics aware back end of line (BEOL) S-parameter model is extracted and seamlessly integrated into the schematic testbench, considering the actual circuit as a black box and therefore actively cutting down the design's netlist size to minimum values. Thus, the DC - DC converter performance degradation, that previously could not be simulated, now is accurately predicted and evaluated while the respective simu-lation time and the number of design iterations needed from layout (physical design) to the schematic and vice versa, are minimized. The proposed methodology is validated using an Integrated Pulse Width Modulation controlled DC -DC converter product vehicle, for light energy harvesting applications, designed, simulated and fabricated in a 0.18 mu m CMOS standard process. Experimental results confirm the accuracy and design cycle speed up effectiveness of the proposed novel IC power converter design methodology.

Automated summary

A novel design methodology is developed to speed up the design cycle time of DC-DC power converters. This methodology provides high accuracy post-layout RC parasitics aware results by using small signal approximation models instead of complicated large RC netlists. Scattering parameters analysis is used for on the fly performance simulation of the power MOSFET switches' routings. The proposed methodology integrates the RC parasitics aware back end of line (BEOL) S-parameter model into the schematic testbench, minimizing the design's netlist size. This methodology accurately predicts and evaluates the performance degradation of the DC-DC converter, which was previously unable to be simulated, while reducing the simulation time and design iterations needed.