Related references
Note: Only part of the references are listed.A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications
Tsung-Yung Jonathan Chang et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2021)
A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell-Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue
Hidehiro Fujiwara et al.
2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) (2021)
Reliable write assist low power SRAM cell for wireless sensor network applications
Soumitra Pal et al.
IET CIRCUITS DEVICES & SYSTEMS (2020)
A 23.6-Mb/mm2 SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications
Zheng Guo et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2019)
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
Shourya Gupta et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2019)
Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications
Vishal Sharma et al.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS (2019)
Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications
Sayeed Ahmad et al.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS (2018)
iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor
Yiqun Zhang et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2018)
A 2.7 pJ/cycle 16 MHz, 0.7 μW Deep Sleep Power ARM Cortex-M0+Core SoC in 28 nm FD-SOI
Guenole Lallement et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2018)
A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications
Yung-Chen Chien et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2018)
A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability
De-bin Kong et al.
IEICE ELECTRONICS EXPRESS (2018)
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
Naeem Maroof et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2017)
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation
Mahmut E. Sinangil et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2016)
A Subthreshold ARM Cortex-M0+Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator
James Myers et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2016)
A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations
Ghasem Pasandi et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2015)
Comparison and statistical analysis of four write stability metrics in bulk CMOS static random access memory cells
Hao Qiu et al.
JAPANESE JOURNAL OF APPLIED PHYSICS (2015)
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
Yi-Wei Chiu et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2014)
A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells
Matthew Fojtik et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2013)
Leakage Characterization of 10T SRAM Cell
A. Islam et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2012)
A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation
Benton Highsmith Calhoun et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2007)
Share Paper
