Adaptative Zero-Bit Pattern Scheme for Reducing Energy Consumption of Non-Volatile Memories

Article Engineering, Electrical & Electronic

Exploiting Non-Leading Zeroes to Reduce Energy Consumption for Non-Volatile Memories

Juhee Choi et al.

Summary: The penalty of write operations is a major obstacle for using nonvolatile memory in IoT devices. The read-before-write scheme is proposed to compare all bits to be written with existing values, effectively reducing unnecessary writes. A zero-bit pattern scheme is designed to deactivate certain bit cells during cache access, resulting in a 35.0% decrease in dynamic energy consumption with only 2.3% additional storage.

IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING (2022)

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Proceedings Paper Computer Science, Hardware & Architecture

Virtual Coset Coding for Encrypted Non-Volatile Memories with Multi-Level Cells

Stephen Longofono et al.

Summary: This paper introduces Virtual Coset Coding (VCC) as a workload-independent approach for reducing costly symbol transitions when storing encrypted data, achieving energy-efficient storage. By reducing the frequency of costly bit/symbol transitions during writes of encrypted data, VCC can lower dynamic energy consumption and significantly increase the lifetime of endurance-limited NVMs by combining fault-mitigation and fault-tolerance techniques.

2022 IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA 2022) (2022)

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Article Computer Science, Hardware & Architecture

Improving the Performance of Hybrid Caches Using Partitioned Victim Caching

Sukarn Agarwal et al.

Summary: The article discusses a hybrid STT-RAM-SRAM architecture to address the write latency issue in non-volatile memory technologies, along with proposing a victim cache to retain evicted victims from the hybrid cache for performance improvement and reduction in miss rate.

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS (2021)

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Proceedings Paper Computer Science, Hardware & Architecture

SimiEncode: A Similarity-based Encoding Scheme to Improve Performance and Lifetime of Non-Volatile Main Memory

Suzhen Wu et al.

Summary: This paper introduces SimiEncode, a similarity-based encoding approach that reduces write latency to NVMs, leading to improved lifetime and performance. Results from extensive evaluations show significant advantages over existing approaches.

2021 IEEE 39TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2021) (2021)

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Review Physics, Applied