Adaptative Zero-Bit Pattern Scheme for Reducing Energy Consumption of Non-Volatile Memories

The main hindrances to employing non-volatile memory (NVM) to the embedded system are the extra energy consumption and long latency of switching states of NVM cells. To mitigate these drawbacks, several schemes have been studied based on the read-before-write scheme (RBW), which reduces the number of write operations by skipping writing bits that are the same in the existing values and new values. Thus, they compare all bits before updating the data. However, these studies also need extra read operations for every write operation. To address this problem, a zero-bit pattern scheme is proposed that skips accessing bit cells determined as zero-bits. In addition, the granularity of the zero-bit pattern is dynamically adjusted depending on the pattern of the non-leading zeroes. The results of the experiments show that dynamic energy is reduced by 43.5% with 4.7% storage overhead. (c) 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

Automated summary

A zero-bit pattern scheme is proposed to reduce the energy consumption and latency of non-volatile memory (NVM) in embedded systems. By skipping the access to bit cells determined as zero-bits, this scheme achieves a 43.5% reduction in dynamic energy with a 4.7% storage overhead, as shown by experimental results.