A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter,-258.7-dB FOM, and-75.17-dBc Reference Spur

This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL). The innovative introduction of a differential parallel-series double-edge sampling phase detector (S-PD) achieves a high phase-detection gain and reduces the S-PLL in-band phase noise (PN). Incorporating a transformer-based harmonic-rich shaping voltage-controlled oscillator (VCO), the proposed S-PLL prototyped in a 65-nm CMOS, operates at 3.6 GHz and scores an integrated jitter of 43.1 fsrms integrated from 1 kHz to 100 MHz, it also exhibits a jitter-power figure-of-merit (FOM) of -258.7 dB. The measured reference (REF) spur is -80.34 dBc at f(REF) and -75.17 dBc at 2 f(REF), respectively.

Automated summary

This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL). The introduction of a differential parallel-series double-edge sampling phase detector (S-PD) achieves a high phase-detection gain and reduces the S-PLL in-band phase noise (PN). The proposed S-PLL, implemented in a 65-nm CMOS, operates at 3.6 GHz and has an integrated jitter of 43.1 fsrms integrated from 1 kHz to 100 MHz, as well as a jitter-power figure-of-merit (FOM) of -258.7 dB. The measured reference (REF) spur is -80.34 dBc at f(REF) and -75.17 dBc at 2 f(REF), respectively.