Symbol-Level Detection With Matched Non-Binary LDPC Codes for Position Errors in Racetrack Memories

In racetrack memory (RM), insertion and deletion (ID) errors occur owing to alignment faults; such errors are referred to as position errors (PEs). Recently, several coding schemes for PEs have been proposed based on binary low-density parity-check (BI-LDPC) codes with a joint bit-wise (BW) detection and decoding algorithm. Although these schemes yield promising asymptotic performance, they suffer from unsatisfactory finite-length performance in short block sizes. To address this problem, we propose a novel coding scheme based on non-binary LDPC (NB-LDPC) codes and symbol-wise (SW) detection. The factor graph of the proposed scheme avoids generating cycles between the detector and decoder graphs by leveraging RM's special property that multiple ID errors are caused by PEs simultaneously, which enables the attainment of good finite-length performance while providing fast convergence. With the aim of providing further performance improvement, we also provide an SW extrinsic information transfer chart analysis to design NB-LDPC codes for the proposed scheme.

Automated summary

This paper proposes a novel coding scheme based on non-binary LDPC codes and symbol-wise detection to address the problem of unsatisfactory finite-length performance of previous schemes. The proposed scheme leverages the special property of racetrack memory to avoid generating cycles between the detector and decoder graphs, leading to improved finite-length performance and fast convergence.