4.6 Article

BEOL-Compatible Bilayer Reprogrammable One-Time Programmable Memory for Low-Voltage Operation

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 70, Issue 3, Pages 1042-1047

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2023.3237508

Keywords

Switches; Nonvolatile memory; Memory management; Hafnium oxide; Fuses; Security; Scanning electron microscopy; Nonvolatile memory (NVM); programmable read-only memory (PROM); self-rectified memory; sneak path

Ask authors/readers for more resources

In this work, an engineered submicrometer-scale bilayer stacking in via-type one-time programmable (OTP) memory and self-rectified resistive switching memory (ReRAM) is demonstrated. The study achieves co-existing memory functionality (OTP and ReRAM) while reducing the scaling requirement. It also proposes an electrode-engineered approach for low programming voltage and extensively studies the impact of various factors on the integration capability.
In this work, an engineered submicrometerscale bilayer stacking in via-type one-time programmable (OTP) memory and self-rectified resistive switching memory [resistive random access memory (ReRAM)] is demonstrated. The current development has achieved that co-existing memory functionality (OTP and ReRAM) with mitigating scaling requirement (fuse voltage trending with via size scaling), low fabrication complexity [viafuse vs. gate-dielectric anti-fuse (AF)], and match with the current metal fuse technology (> 2 V). In addition, an electrode engineered has been proposed to realize low programming voltage (similar to 1.9 V) in via-fuse OTP featuring by metal-insulator-metal advanced back-end-of-line (BEOL) process with ruthenium materials. The impact of via-size, programming window, stacked structures, and integration capability has been extensively studied. Our results provide a pathfinding of high density, integration capability, low programming voltage, multifunctionality between programmable read-only memory (PROM), and resistive switching memory co-existing in future embedded applications.

Authors

I am an author on this paper
Click your name to claim this paper and add it to your profile.

Reviews

Primary Rating

4.6
Not enough ratings

Secondary Ratings

Novelty
-
Significance
-
Scientific rigor
-
Rate this paper

Recommended

No Data Available
No Data Available