Cointegration of the TFT-Type AND Flash Synaptic Array and CMOS Circuits for a Hardware-Based Neural Network

An AND-type flash synaptic array is cointegrated with CMOS circuits using a novel fabrication method. Electrical characteristics of the basic circuit blocks required for neural network operation are verified. By reducing the number of masks and fabrication steps required, the proposed fabrication method successfully integrates synaptic array and CMOS peripheral circuits, including integrate-and-fire (I & F) circuits and passive devices, on a single wafer. The proposed fabrication method provides a methodology for the efficient implementation of hardware-based neural networks as well as verification of excellent compatibility of the proposed synaptic array with CMOS technology.

Automated summary

This study proposes and verifies a novel method of integrating an AND-type flash synaptic array with CMOS circuits. By reducing the number of masks and fabrication steps, the proposed method successfully integrates the synaptic array and CMOS peripheral circuits on a single wafer. This research is of great significance for the efficient implementation of hardware-based neural networks.