Methods to Realize Low-BER and High-Reliability RRAM Chip With Fast Page-Forming Capability

Resistive random access memory (RRAM) exhibits advantages, such as high speed, simple structure, and good compatibility with CMOS technology. However, an additional forming step is usually inevitable, which requires cell-by-cell verification and can be very timeconsuming. This article proposes a novel dual-step page forming method that can realize low-current forming and improve a bit error rate (BER). Based on this technique and corresponding circuit, a no-verify page-forming scheme is proposed and can achieve a fast-forming speed of 7.56 Mb/s. Moreover, the impact of parameters, such as forming voltage and forming time in the forming process on the BER, is discussed. In addition, to achieve lower BER and better reliability, a two-transistor-two-resistor (2T2R) cell structure is adopted, and both digital verify (DV) and analog verify (AV) methods are proposed. The proposed page-forming and two verify methods are experimentally validated on a 1-MB RRAM chip. An ultralow BER of 10(-5)/10(-6) (DV/AV) without any error correction is achieved. Excellent endurance (> 107 cycles for both AV and DV) and retention (> 10 years at 25 ?C for AV) are also demonstrated on the chip level. Overall, this work demonstrates a useful strategy to design high reliability RRAM chip with excellent memory performance.

Automated summary

This article proposes a novel dual-step page forming method that can realize low-current forming and improve a bit error rate (BER). Based on this technique, a no-verify page-forming scheme is proposed and can achieve a fast-forming speed of 7.56 Mb/s.