Highly Linear Analog Spike Processing Block Integrated With an AND-Type Flash Array and CMOS Neuron Circuits

In this article, a highly linear spike processing block (SPB) integrating AND-type charge-trap flash (CTF) synapse array (25 x 4 synapses) and CMOS integrate-and-fire (IF) neurons is fabricated for hardware-based spiking neural networks (SNNs). We investigate the synaptic behavior of the CTF cells and the operating principle of the neuron circuits. Under the given operating conditions, the fabricated SPB consistently exhibits a highly linear relationship (R-2 > 0.999) between the current sum and the output spike frequency, enabling the SNNs to precisely mimic the layer of artificial neural networks (ANNs) with rectified linear unit (ReLU) activation function. Based on the fabricated SPB, a single-layer SNN is experimentally demonstrated for classifying the 5 x 5 digit patterns.

Automated summary

In this article, a highly linear spike processing block (SPB) integrating AND-type charge-trap flash (CTF) synapse array and CMOS integrate-and-fire (IF) neurons is fabricated for hardware-based spiking neural networks (SNNs). The SPB exhibits a highly linear relationship between the current sum and the output spike frequency, enabling precise mimicry of artificial neural networks with ReLU activation function. A single layer SNN is experimentally demonstrated for classifying digit patterns.