Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 69, Issue 11, Pages 6065-6071Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2022.3207707
Keywords
AND-type array; charge-trap flash (CTF); integrate-and-fire(IF) neuron; neuromorphic; spike processing block (SPB); spiking neural networks (SNNs)
Funding
- BK21 FOUR Program of the Education and Research Program for Future ICT Pioneers, Seoul National University
- National Research Foundation of Korea (NRF), Ministry of Science and ICT [2021M3F3A2A02037889]
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In this article, a highly linear spike processing block (SPB) integrating AND-type charge-trap flash (CTF) synapse array and CMOS integrate-and-fire (IF) neurons is fabricated for hardware-based spiking neural networks (SNNs). The SPB exhibits a highly linear relationship between the current sum and the output spike frequency, enabling precise mimicry of artificial neural networks with ReLU activation function. A single layer SNN is experimentally demonstrated for classifying digit patterns.
In this article, a highly linear spike processing block (SPB) integrating AND-type charge-trap flash (CTF) synapse array (25 x 4 synapses) and CMOS integrate-and-fire (IF) neurons is fabricated for hardware-based spiking neural networks (SNNs). We investigate the synaptic behavior of the CTF cells and the operating principle of the neuron circuits. Under the given operating conditions, the fabricated SPB consistently exhibits a highly linear relationship (R-2 > 0.999) between the current sum and the output spike frequency, enabling the SNNs to precisely mimic the layer of artificial neural networks (ANNs) with rectified linear unit (ReLU) activation function. Based on the fabricated SPB, a single-layer SNN is experimentally demonstrated for classifying the 5 x 5 digit patterns.
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