Pragmatic Memory-System Support for Intermittent Computing Using Emerging Nonvolatile Memory

Intermittent computing (IC) is a key enabler for the vision of a trillion Internet of Things devices. By harvesting energy from the environment and leveraging nonvolatile memory (NVM) to retain computational progress across power cycles, IC enables untethered and battery-free devices to perform computation whenever ambient energy is available. The backbone of state retention is NVM, and recent advances in energy-efficient NVM have the potential to expand the application domain of IC significantly. Utilizing emerging NVM at the level of bit cells, researchers have proposed nonvolatile processors. However, these do not leverage hardware-software co-design, which can be used to overcome hardware limitations and to provide support for application-level constraints such as atomicity. In this article, we propose MEMIC, a memory architecture tailored for IC devices with byte-addressable NVM. A core focus of MEMIC is to combine volatile and NVM in such a way that the operations of IC are as efficient as possible, while also maximizing computational performance per joule. MEMIC uses volatile memory for energy efficiency and NVM for data retention. To avoid double-buffered checkpoints and costly roll backs when code needs to be reexecuted, MEMIC is designed to track and minimize writes to NVM during failure-atomic sections. Our evaluation shows that MEMIC's instruction cache reduces workload completion time under intermittent operation by 41%-70% and its data cache provides a further reduction of 13%-39%.

Automated summary

Intermittent computing is essential for the Internet of Things, allowing devices to perform computation using harvested energy when available. Nonvolatile memory is crucial for retaining computational progress across power cycles. MEMIC is a memory architecture designed for intermittent computing devices, combining volatile and nonvolatile memory efficiently to maximize computational performance per joule. MEMIC's instruction and data cache greatly reduce workload completion time under intermittent operation.