XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

Automated summary

This brief presents a energy-efficient and high-performance XNOR-bitcount architecture using computing-in-memory (CiM) and spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Hardware and algorithmic optimizations are proposed and benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that the hardware optimization reduces the storage requirement for each XNOR-bitcount operation by 50%, while the algorithmic optimization improves execution time and energy consumption by about 30% and 26%, respectively, for single and sequential 9-bit XNOR-bitcount operations. A case study on shape analysis using bit-quads is demonstrated.