Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 69, Issue 12, Pages 4644-4648Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2022.3184774
Keywords
Low dropout regulator (LDO); adaptive sampling; voltage-controlled oscillator; subthreshold current; symmetric frequency generation
Categories
Funding
- Japan Society for the Promotion of Science (JSPS) KAKENHI through the activities of VDEC, University of Tokyo
- Synopsys, Inc. [19K20233]
- Rohm Joint Research Program
Ask authors/readers for more resources
This study proposes a digital LDO solution that achieves fast transient response and low power operation by using a built-in non-linear VCO. The solution generates a clock signal with a non-linear symmetric function based on the output voltage error, resulting in low power consumption and symmetric frequency generation.
This brief proposes a digital LDO (Low DropOut regulator) with a built-in non-linear VCO (Voltage Controlled Oscillator) to achieve both the fast transient response and low power operation. This on-chip VCO generates a clock signal whose frequency is a non-linear symmetric function of the output voltage error. Here, we propose a design technique to realize the symmetric frequency generation with low power consumption. We demonstrate a design example of LDO using our proposed technique in a commercial 65 nm low-power CMOS process. We evaluate the LDO using transistor-level simulation using HSPICE. It achieves 0.03-11 mu A of quiescent current with an input voltage range of 0.6-1.2 V and an average current efficiency of 99.68% across 50x load range.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available