Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 69, Issue 12, Pages 4944-4957Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2022.3201016
Keywords
Calibration; Nonlinear distortion; Artificial neural networks; Integrated circuit modeling; Silicon; Phase distortion; Mathematical models; Analog-to-digital converter (ADC); nonlinear digital calibration; neural network; static and dynamic calibrations; compute-in-memory
Categories
Funding
- National Natural Science Foundation of China (NSFC) [62074038]
- Science and Technology Innovation [2021ZD0114400]
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This paper introduces a neural network-based digital calibration algorithm for high-speed and time-interleaved ADCs. The algorithm is able to correct both amplitude-dependent and phase-dependent nonlinear distortion without prior knowledge of the ADC architecture. Experimental results demonstrate that the algorithm significantly improves the performance of the ADCs.
This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent and phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic calibration is first used to compensate for phase-dependent distortion. Two training optimizations, including a sub-range-sample-based batch schemes and a recursive foreground co-calibration flow are proposed to reduce the error and overfitting and further save hardware resources. A practical calibration engine is also investigated for interleaved ADCs with distributed weight and shared weight methods. To demonstrate the effectiveness of the method, the calibration engine is verified by two fabricated ADC prototypes, a 5 GS/s 16-way interleaved ADC and a 625 MS/s interleaving-SAR assisted pipeline ADC. Measurement results show that SFDR is improved between 16.9dB and 36.4dB before and after calibration for different frequency inputs. To trade-off between accuracy and power consumption, a quantized and pruned engine is implemented on both FPGA and 28nm CMOS technology. Experimental results show that the dedicated calibration on silicon consumes 8.64mW with 0.9V power supply at 333MHz clock rate. Measurement results show that the quantized hardware implementation has only 0.4-4 dB loss in SFDR.
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