Analysis and Calibration for Wideband Times-2 Interleaved Current-Steering DACs

This work presents analysis and calibration of interleaving and data timing errors that are encountered in modern times-2 interleaved digital-to-analog converters (DACs) with a current-steering (CS) architecture. Such errors corrupt the DAC output spectrum with spectral images that require calibration. We develop an analytical model for the interleaving and data timing errors that we understand are most significant and propose a calibration algorithm that treats all of them. Extensive simulations of the algorithm are made possible by leveraging the speed and accuracy of the analytical model. The algorithm is demonstrated on a commercially-developed 10-bit times-2 interleaved CS-DAC, operating at 40GS/s in 14nm CMOS.

Automated summary

This work presents an analysis and calibration of interleaving and data timing errors in modern times-2 interleaved digital-to-analog converters. The authors develop an analytical model and propose a calibration algorithm to address these errors. Extensive simulations using the model demonstrate the effectiveness of the algorithm.