QCA-Based PIPO and SIPO Shift Registers Using Cost-Optimized and Energy-Efficient D Flip Flop

With the growing use of quantum-dot cellular automata (QCA) nanotechnology, digital circuits designed at the Nanoscale have a number of advantages over CMOS devices, including the lower utilization of power, increased processing speed of the circuit, and higher density. There are several flip flop designs proposed in the literature with their realization in the QCA technology. However, the majority of these designs suffer from large cell counts, large area utilization, and latency, which leads to the high cost of the circuits. To address this, this work performed a literature survey of the D flip flop (DFF) designs and complex sequential circuits that can be designed from it. A new design of D flip flop was proposed in this work and to assess the performance of the proposed QCA design, an in-depth comparison with existing designs was performed. Further, sequential circuits such as parallel-in-parallel-out (PIPO) and serial-in-parallel-out (SIPO) shift registers were designed using the flip flop design that was put forward. A comprehensive evaluation of the energy dissipation of all presented fundamental flip-flop circuits and other sequential circuits was also performed using the QCAPro tool, and their energy dissipation maps were also obtained. The suggested designs showed lower power dissipation and were cost-efficient, making them suitable for designing higher-power circuits.

Automated summary

This study investigated the design of D flip flops in QCA technology and proposed a new design, which showed lower power dissipation and cost efficiency. The performance was assessed through comparisons with existing designs, and the energy dissipation of all presented circuits was evaluated using the QCAPro tool.