4.6 Article

On Noise Modeling of Capacitive Feedback Transimpedance Amplifiers in CMOS

Journal

APPLIED SCIENCES-BASEL
Volume 12, Issue 19, Pages -

Publisher

MDPI
DOI: 10.3390/app121910186

Keywords

capacitive feedback; CMOS integrated circuits; low-noise amplifiers; noise modeling; optical time-domain reflectometry; transimpedance amplifiers

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This paper presents the development of a detailed noise current model for a low-noise capacitive feedback transimpedance amplifier (TIA) in CMOS, including a spectral density model for input-related noise. The performance of the proposed model is evaluated through post-layout simulation, showing important noise components present in practical circuits that were previously omitted in known noise models.
The work reports on the development of a detailed noise current model for a low-noise capacitive feedback transimpedance amplifier (TIA) in CMOS. The proposed TIA circuit implements the programmable-gain using an array of discretely controlled feedback capacitors and resistances in the biasing circuit and is originally designed bearing in mind low-noise requirements for optical time-domain reflectometer (OTDR) applications with the base gain of 10 k Omega at 1 GHz bandwidth and noise levels below 5.0 pA/root Hz. The newly developed model for input-referred noise current spectral density complements the previously suggested transimpedance gain model and takes into account both the primary and secondary noise sources so far ignored in the models known in the literature. The proposed noise model consists of five terms and includes the effects caused by biasing components of the input stage and the noise shaping from the source follower. The performance of the developed noise model is evaluated using the post-layout simulation in 0.18 mu m CMOS and 0.25 mu m BiCMOS technologies, and a close match of the proposed model is demonstrated in the results of the post-layout simulation with the noise level below 1.8 pA/root Hz for the base gain configuration in CMOS. A comparison to available noise models from the literature confirms that previously known noise models for this promising TIA architecture omitted important noise components present in practical and physically realizable circuits and, therefore, resulted in underestimating the base noise level by a factor of two to three, while completely ignoring the flicker noise mapping in the low-frequency range.

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