4.7 Article

Simulation of Figures of Merit for Barristor Based on Graphene/Insulator Junction

Journal

NANOMATERIALS
Volume 12, Issue 17, Pages -

Publisher

MDPI
DOI: 10.3390/nano12173029

Keywords

graphene; barristor; Fowler-Nordheim tunneling; cut-off frequency; delay time; power-delay product

Funding

  1. National Research Foundation of Korea (NRF) - Korean government (MIST) [2020R1A2C1003398]
  2. Korea Basic Science Institute(National research Facilities and Equipment Center) - Ministry of Education [2022R1A6C101A754]
  3. National Research Foundation of Korea [2022R1A6C101A754, 2020R1A2C1003398] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

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This study investigates the tunneling of graphene/insulator/metal heterojunctions by revising the Tsu-Esaki model and direct tunneling current. The study shows that the revised equations for both tunneling currents are proportional to V-3, which is due to the linear dispersion of graphene. A simulation tool is developed using MATLAB with the revised tunneling equations. The device performance of the field-emission barristor is optimized by engineering the barrier height and thickness, improving the delay time, cut-off frequency, and power-delay product.
We investigated the tunneling of graphene/insulator/metal heterojunctions by revising the Tsu-Esaki model of Fowler-Nordheim tunneling and direct tunneling current. Notably, the revised equations for both tunneling currents are proportional to V-3, which originates from the linear dispersion of graphene. We developed a simulation tool by adopting revised tunneling equations using MATLAB. Thereafter, we optimized the device performance of the field-emission barristor by engineering the barrier height and thickness to improve the delay time, cut-off frequency, and power-delay product.

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