Low-power hardware-efficient memory-based DCT processor

This paper proposes a new discrete cosine transform (DCT) processor. The micro-rotation section of the architecture is based on a shared-resource improved coordinate rotation digital computer (CORDIC) unit, in an enhanced scalable DCT engine. To reduce the resources, and utilization area all micro-rotation operations have implemented as one united block in overlapped form. Using one processing element, the memory-based architecture has reduced the power consumption. Inputs and outputs of the processor are in-order which can be taken into account as an advantage for the proposed design. The processor has a low-complexity and distributed controller. Furthermore, due to the shared-resource implementation of CORDIC-II unit, by reduction of adding, shifting operations both in size, and number, the processor has high capabilities in short word lengths in comparison with state-of-the-art DCT processors. Compared to existing prominent DCT processors, the proposed processor achieves better results with limited hardware resources.

Automated summary

This paper proposes a new discrete cosine transform (DCT) processor that utilizes a shared-resource improved coordinate rotation digital computer (CORDIC) unit to implement micro-rotation operations, reducing resource requirements and power consumption. The processor features in-order inputs and outputs, low complexity, and a distributed controller, making it capable of achieving high performance with short word lengths compared to state-of-the-art DCT processors. The proposed processor outperforms existing prominent DCT processors with limited hardware resources.