4.6 Article

Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applications

Journal

SOFT COMPUTING
Volume 27, Issue 7, Pages 4289-4306

Publisher

SPRINGER
DOI: 10.1007/s00500-022-07371-7

Keywords

BCH code; Digital filters; Error detection and correction; FIR filters; FPGA; Soft errors; Triple modular redundancy

Ask authors/readers for more resources

Digital filters are widely used in signal processing, but soft errors can affect their reliability. This study proposes fault-tolerant digital filters that can correct single and double errors using soft computing approaches. Experimental results show that the proposed method outperforms traditional methods in terms of resource utilization, implementation cost, and protection.
Digital filters are increasingly being used in signal processing areas. The soft errors present in these circuits are found to affect the reliability of the systems such as biomedical and space applications. In this work, fault-tolerant digital finite impulse response (FIR) filters are designed to have the same impulse response that process different input signals and multiple responses with constant input signals using the soft computing approaches. The soft computing approaches used in the proposed FIR filters are Bose-Chaudhuri-Hocquenghem (BCH) code for single error correction and double error correction. The performance of the proposed method is evaluated by considering different FIR filter tap configurations. The Questasim simulator has been used to validate the functionality of the designed modules using a Verilog HDL. The Xilinx Vivado HLx 2018.3 and Artix-7 xc7a200 and Virtex-4 XC4VLX80 FPGA devices have been used for synthesis and implementation. Significant savings up to 28.02% and 21.8%, 26.67% and 26.33% of different field programmable gate array (FPGA) architecture resources like Slices, LUTs, flip-flops, and LUTRAMs for the parallel filters having the same impulse response and different impulse responses, respectively, are achieved as compared to the triple modular redundancy method. The digital parallel FIR filters implemented with FPGA shows effectiveness in terms of correction of single and double errors by employing the BCH code, implementation cost, and protection.

Authors

I am an author on this paper
Click your name to claim this paper and add it to your profile.

Reviews

Primary Rating

4.6
Not enough ratings

Secondary Ratings

Novelty
-
Significance
-
Scientific rigor
-
Rate this paper

Recommended

No Data Available
No Data Available