A 14-bit 1.2-V low power SAR ADC with digital background calibration in 0.18 μm CMOS

A 14-bit successive-approximation-register analog-to-digital converter is proposed for intelligent sensing application. A redundant integer sub-radix-2 capacitor array is adopted to recover the conversion errors. The capacitor mismatch is further mitigated with the digital background calibration. Different from the previous calibration that requires two ADC channels, the calibration approach is based on a single ADC, resulting in a considerable area reduction. The input signal injected with two different values are successively quantized twice by this ADC, and then digital background calibration is performed with these two output data. Designed with a 0.18 mu m CMOS technology, the proposed SAR ADC occupies an area of 0.5682 mm2. The design results indicate that the SAR ADC can achieve a signal-to-noise distortion ratio of 77.6 dB and a spurious-free dynamic range of 108.5 dB at the sampling rate of 125 kS/s with the capacitor mismatch of 5%. The power consumption is 24.1 mu W and the corresponding figure of merit (FoM) is 71.0 fJ/Conversion-step at 1.2 V.

Automated summary

This paper proposes a 14-bit successive-approximation-register analog-to-digital converter for intelligent sensing applications. It adopts a redundant integer sub-radix-2 capacitor array to recover the conversion errors and mitigates the capacitor mismatch with digital background calibration. Unlike previous calibration methods that require two ADC channels, this approach only needs a single ADC, resulting in a significant area reduction.