4.5 Article

ReNo: novel switch architecture for reliability improvement of NoCs

Journal

JOURNAL OF SUPERCOMPUTING
Volume 79, Issue 3, Pages 2801-2818

Publisher

SPRINGER
DOI: 10.1007/s11227-022-04732-9

Keywords

Network-on-Chip; Fault; Reconfiguration; Switch

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This study proposes a new reconfigurable switch architecture called ReNo to enhance the resilience of NoCs against transient faults. The architecture utilizes a local configuration controller logic to adjust the switch's reliability mode based on error rates, minimizing performance and power overheads. Simulation results demonstrate significant reliability improvement and at least 20% performance and power saving compared to existing mechanisms.
Using of nano-scale Very Large-Scale Integration technologies in Network-on-Chips (NoCs), switches and communication wires of NoCs are sensitive to transient faults. In the architecture of NoCs, switches play an important role in the correct and reliable functions of NoCs against transient faults. The most important transient faults in NoCs are crosstalk faults in wires and Single Event Upset (SEU) and Multipl Event Upset (MBU) faults in buffers. In order to provide reliable switch, we propose a new reconfigurable switch architecture named ReNo to make NoCs more resilience to transient faults. ReNo is able to work in four configurations with several levels of reliability. As a result, local configuration controller logic is used to preserve against transient faults. In ReNo architecture, when a controller finds a high error rate, it configures the switch to a high reliability mode. In this way, imposed performance and power overheads to the switch are minimized. Simulation results which are obtained by Orion patch for power estimation show a significant reliability improvement with a meager performance and power saving at least 20% is achieved in proposed switch architecture, with improvement to state-of-the-art mechanisms.

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