Journal
INTEGRATION-THE VLSI JOURNAL
Volume 87, Issue -, Pages 205-210Publisher
ELSEVIER
DOI: 10.1016/j.vlsi.2022.08.005
Keywords
SAR ADC; Digital calibration; High-resolution; CDAC
Funding
- Young Scientists Fund of the Na- tional Natural Science Foundation of China [62004115]
- Young Scientists Fund of Shandong Provincial Natural Science Foundation [ZR2020QF023]
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This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. The prototype exhibits excellent performance with high figure of merit, effective number of bits, and dynamic range.
This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-mu m CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are-0.422/0.536 LSB and-0.721/0.758 LSB, respectively.
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