Journal
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
Volume 16, Issue 4, Pages 636-650Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TBCAS.2022.3189240
Keywords
Neurons; Neuromorphics; Hardware; System-on-chip; Field programmable gate arrays; Synapses; Self-organizing feature maps; Neuromorphic system; spiking neural network; spike-timing dependent plasticity; self-organizing map; reinforce- ment learning; on-chip learning
Funding
- National Key Research and Development Program of China [2019YFB2204303]
- National Natural Science Foundation of China [U20A20205]
- Key Project of Chongqing Science and Technology Foundation [cstc2019jcyj-zdxmX0017, cstc2021ycjh-bgzxm0031]
- Chongqing Xianfeng Electronic Institute Co., Ltd through Pilot Research Project [H20201100]
- State Key Laboratory of Computer Architecture, ICT, CAS [CARCH201908]
- Chongqing Social Security Bureau and Human Resources Dept. [cx2020018]
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The researchers proposed a new neuromorphic hardware core called TripleBrain, which combines multiple brain-inspired computing paradigms. This core improves object recognition accuracy and processing speed while consuming low resources. Through FPGA prototype testing, the core achieved high-speed learning and inference with comparably high recognition accuracies on multiple datasets.
Human brain cortex acts as a rich inspiration source for constructing efficient artificial cognitive systems. In this paper, we investigate to incorporate multiple brain-inspired computing paradigms for compact, fast and high-accuracy neuromorphic hardware implementation. We propose the TripleBrain hardware core that tightly combines three common brain-inspired factors: the spike-based processing and plasticity, the self-organizing map (SOM) mechanism and the reinforcement learning scheme, to improve object recognition accuracy and processing throughput, while keeping low resource costs. The proposed hardware core is fully event-driven to mitigate unnecessary operations, and enables various on-chip learning rules (including the proposed SOM-STDP & R-STDP rule and the R-SOM-STDP rule regarded as the two variants of our TripleBrain learning rule) with different accuracy-latency tradeoffs to satisfy user requirements. An FPGA prototype of the neuromorphic core was implemented and elaborately tested. It realized high-speed learning (1349 frame/s) and inference (2698 frame/s), and obtained comparably high recognition accuracies of 95.10%, 80.89%, 100%, 94.94%, 82.32%, 100% and 97.93% on the MNIST, ETH-80, ORL-10, Yale-10, N-MNIST, Poker-DVS and Posture-DVS datasets, respectively, while only consuming 4146 (7.59%) slices, 32 (3.56%) DSPs and 131 (24.04%) Block RAMs on a Xilinx Zynq-7045 FPGA chip. Our neuromorphic core is very attractive for real-time resource-limited edge intelligent systems.
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