4.7 Article

A 0.6-V 94-nW 10-Bit 200-kS/s Single-Ended SAR ADC for Implantable Biosensor Applications

Journal

IEEE SENSORS JOURNAL
Volume 22, Issue 18, Pages 17904-17913

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSEN.2022.3195632

Keywords

Comparator; implantable biosensor applications; low offset; low power; successive approximation register (SAR) analog-to-digital converter (ADC); switching scheme

Funding

  1. National Natural Science Foundation of China [62021004, 62090043, 61904133, 61974109]
  2. Fundamental Research Funds for the Central Universities [YJS2213]
  3. Innovation Fund of Xidian University

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This work presents an ultralow-power ADC for implantable biosensor applications, featuring high energy efficiency, area efficiency, and low offset noise.
This work presents an ultralow-power 10-bit 200-kS/s single-ended successive approximation register (SAR) analog-to-digital converter (ADC) for implantable biosensor applications. A high energy- and area-efficient switching scheme is proposed, which realizes 95.4% energy saving in a digital-to-analog converter (DAC) switching and two times DAC area reduction compared to the conventional single-ended SAR ADC. The common-mode variation in the proposed scheme is input-independent, resulting in a reduced dynamic offset and harmonic distortion. Besides, a low offset and low kickback noise dynamic comparator with P-type input pair is realized. The prototype is fabricated in 65-nm CMOS technology, consuming 94 nW at 0.6-V supply and occupying a 0.02-mm(2) active area. With the Nyquist input frequency, it achieves the signal to noise and distortion ratio (SNDR) of 56.42 dB, leading to a Walden figure of merit (FoM) of 0.87 fJ/conv.-step.

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