Vertical C-Shaped-Channel Nanosheet FETs Featured With Precise Control of Both Channel-Thickness and Gate-Length

Article Engineering, Electrical & Electronic

Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs

Natalia Seoane et al.

Summary: Metal grain granularity and line-edge roughness are the main sources of variability affecting device performance, with nanosheets and nanowires being more affected by MGG variability and less affected by LER variability.

IEEE ELECTRON DEVICE LETTERS (2021)

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Article Engineering, Electrical & Electronic

Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process

Yongkui Zhang et al.

Summary: The study presented a new type of vertical nanowire and nanosheet field-effect transistors (FETs) called VSAFETs, fabricated with a specific process, suitable for producing high-performing p-type NS and NW VSAFETs.

IEEE TRANSACTIONS ON ELECTRON DEVICES (2021)

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Article Chemistry, Multidisciplinary

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates

Chen Li et al.

Summary: This paper introduces a novel n-type nanowire/nanosheet (NW/NS) vertical sandwich gate-all-around field-effect-transistor (nVSAFET) which aims at achieving a 3 nm technology node and beyond by utilizing self-aligned and replaced high-kappa metal gates (HKMGs). The fabrication process is CMOS-compatible, simple, and reproducible, resulting in nanowires with a diameter of 17 nm and nanosheets with a thickness of 20 nm. The proposed integration scheme shows great potential for chip manufacturing applications, particularly in vertical channel devices.

NANO LETTERS (2021)

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Proceedings Paper Engineering, Electrical & Electronic

Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

H. Jagannathan et al.

Summary: Vertical-Transport Nanosheet (VTFET) CMOS logic transistors at sub-45nm gate pitch on bulk silicon wafers present a breakthrough in overcoming the Contacted Gate Pitch (CGP) barrier, offering scaling relief for electrostatics and parasitics. Innovative device characteristics and design strategies demonstrate improved performance and logic area scaling advantages.

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) (2021)

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Article Engineering, Electrical & Electronic