Journal
IEEE ELECTRON DEVICE LETTERS
Volume 43, Issue 8, Pages 1183-1186Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2022.3187006
Keywords
Vertical C-shaped-channel nanosheet FET; VCNFET; nanosheet; I-on/I-off ratio; 3D monolithic integration
Categories
Funding
- Process Development under Beijing Superstring Academy Memory Technology [SAMTZK-CFA1-21060302]
- Vertical Gate-All-Around (GAA) for Dynamic Random Access Memory (DRAM)
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In this work, a novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) with precise control of channel thickness and gate length, and a unique integration flow of Dual Side Process (DSP) is proposed. The VCNFETs are fabricated using high quality Si/SiGe epitaxy, atomic layer etching, and self-aligned high-k metal gate (HKMG). The integration flow is compatible with mainstream CMOS technology. The device exhibits excellent performance with perfect subthreshold slope (SS), small drain-induced barrier lowering (DIBL), and remarkably large on/off ratio.
A novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) featured with precise control of channel-thickness and gate-length, and a unique integration flow of Dual Side Process (DSP) are proposed in this work. The VCNFETs were fabricated by high quality Si/SiGe epitaxy, atomic layer etching with nanometer-scale process control and self-aligned high-k metal gate (HKMG). The integration flow is compatible with mainstream CMOS technology. Thanks to the precise control of channel thickness and doping profiles, perfect SS of 61 mV/dec, small DIBL of 8 mV/V, and remarkably large I-on/I-off ratio of 6.28 x 10(9) were achieved. The device performance and it's optimization were also investigated with the reduction of the external resistance and numerical simulations.
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