A 0.6-1.8 V/0.4-1.6 V Input/Output LDO with High PSRR over 50 dB/30 dB in Dual-Modes

A output-capacitorless, wide range 0.6-1.8 V/0.4-1.6 V input/output, dual-mode low-dropout regulator with a high-power supply rejection ratio (PSRR) is proposed in this paper. When the input voltage is higher than 1.2 V, the high-voltage mode (HVM) is activated and the input can be directly used in the proposed LDO with high PSRR and high stability. If the input voltage drops below 1.2 V, LDO would be working stably by the charge pump and internal voltage-controlled oscillator in low-voltage mode (LVM). Meanwhile, linearity and load regulations can also be improved through the proposed sub-amplifier transconductance-enhancement compensation method and high-speed transconductance buffer. The verification of design is completed under a standard 0.18 mu m CMOS process. The simulation results show that output voltage ranges from 0.4 to 1.6 V while input ranges from 0.6 to 1.8 V, and proposed LDO remains over 50 dB PSRR in HVM mode and 30 dB in LVM mode.

Automated summary

This paper proposes a dual-mode low-dropout regulator with a wide input/output voltage range and high-power supply rejection ratio. The regulator can operate in high-voltage mode and low-voltage mode, ensuring stable performance. The proposed design also utilizes a compensation method and a buffer to improve linearity and load regulation performance.