4.8 Article

Reconfigurable heterogeneous integration using stackable chips with embedded artificial intelligence

Journal

NATURE ELECTRONICS
Volume 5, Issue 6, Pages 386-393

Publisher

NATURE PORTFOLIO
DOI: 10.1038/s41928-022-00778-y

Keywords

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Funding

  1. Ministry of Trade, Industry and Energy (MOTIE), South Korea by the Korea Institute for Advancement of Technology (KIAT) [P0008749]
  2. Korea Institute of Science and Technology (KIST) [2E31550]
  3. Samsung Global Research Outreach (GRO) Program
  4. Ministry of Health & Welfare (MOHW), Republic of Korea [P0008749] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
  5. National Research Foundation of Korea [2E31550] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

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Artificial intelligence applications have driven the search for efficient hardware architecture that can process large amounts of data. This study introduces stackable hetero-integrated chips using optoelectronic device arrays and memristor crossbar arrays for high parallel data processing and classification.
Artificial intelligence applications have changed the landscape of computer design, driving a search for hardware architecture that can efficiently process large amounts of data. Three-dimensional heterogeneous integration with advanced packaging technologies could be used to improve data bandwidth among sensors, memory and processors. However, such systems are limited by a lack of hardware reconfigurability and the use of conventional von Neumann architectures. Here we report stackable hetero-integrated chips that use optoelectronic device arrays for chip-to-chip communication and neuromorphic cores based on memristor crossbar arrays for highly parallel data processing. With this approach, we create a system with stackable and replaceable chips that can directly classify information from a light-based image source. We also modify this system by inserting a preprogrammed neuromorphic denoising layer that improves the classification performance in a noisy environment. Our reconfigurable three-dimensional hetero-integrated technology can be used to vertically stack a diverse range of functional layers and could provide energy-efficient sensor computing systems for edge computing applications. By using optoelectronic device arrays for chip-to-chip communication and neuromorphic cores based on memristor crossbar arrays for highly parallel data processing, reconfigurable and stackable hetero-integrated chips can be created for use in edge computing applications.

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