Related references
Note: Only part of the references are listed.A TCAD Study on Lateral Power MOSFET With Dual Conduction Paths and High- $k$ Passivation
Junji Cheng et al.
IEEE ELECTRON DEVICE LETTERS (2020)
Reliability Concerns on LDMOS With Different Split-STI Layout Patterns
Ran Ye et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2020)
Novel SiC/Si heterojunction LDMOS with electric field modulation effect by reversed L-shaped field plate
Qi Li et al.
RESULTS IN PHYSICS (2020)
Reducing specific on-resistance for a trench SOI LDMOS with L-shaped P/N pillars
Jingwei Guo et al.
RESULTS IN PHYSICS (2020)
Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers
Yuan Wang et al.
RESULTS IN PHYSICS (2020)
Performance analysis of a novel trench SOI LDMOS with centrosymmetric double vertical field plates
Jianmei Lei et al.
RESULTS IN PHYSICS (2019)
Analytical Model for the SOI Lateral Power Device With Step Width Technique and High-k Dielectric
Jiafei Yao et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2019)
Potential of Utilizing High-k Film to Improve the Cost Performance of Trench LDMOS
Junji Cheng et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2019)
Numerical investigation on L-shaped vertical field plate in high-voltage LDMOS
Yue Hu et al.
RESULTS IN PHYSICS (2019)
Equivalent model and limit for the SOI lateral power device using high-k dielectric
Jiafei Yao et al.
RESULTS IN PHYSICS (2019)
A novel SOI LDMOS with substrate field plate and variable-k dielectric buried layer
Qi Li et al.
RESULTS IN PHYSICS (2018)
An improved SOI trench LDMOST with double vertical high-k insulator pillars
Huan Li et al.
JOURNAL OF SEMICONDUCTORS (2018)
Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal-Oxide-Semiconductor Transistors Using High-k Dielectric
Yufeng Guo et al.
IEEE ELECTRON DEVICE LETTERS (2015)
Analysis and Fabrication of an LDMOS With High-Permittivity Dielectric
Junhong Li et al.
IEEE ELECTRON DEVICE LETTERS (2011)
High Permittivity Dielectric LDMOS for Improved Performance
Junhong Li et al.
PROCEEDINGS OF INTERNATIONAL CONFERENCE ON SMART GRID AND CLEAN ENERGY TECHNOLOGIES (ICSGCE 2011) (2011)
Partial SOI Power LDMOS With a Variable Low-k Dielectric Buried Layer and a Buried P Layer
Xiaorong Luo et al.
IEEE ELECTRON DEVICE LETTERS (2010)
Novel Low-k Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI
Xiaorong Luo et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2010)
A new analytical model for optimizing SOI LDMOS with step doped drift region
Yufeng Guo et al.
MICROELECTRONICS JOURNAL (2006)
Share Paper
