Journal
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
Volume 22, Issue 3, Pages 188-197Publisher
IEEK PUBLICATION CENTER
DOI: 10.5573/JSTS.2022.22.3.188
Keywords
CMOS; nanoelectromechanical (NEM) memory switch; memory switch; monolithic three-dimensional (M3D) integration; integration; field programmable gate array (FPGA)
Funding
- NRF of Korea - MSIT [NRF-2021M3F3A2A01037927, NRF-2022M3F3A2A01073944, NRF-2022M3I7A1078544, NRF-2021R1A2C1007931]
- National Research Foundation of Korea [2022M3I7A1078544] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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Research on NEM devices for logic and memory applications has been reviewed in the context of monolithic 3D (M3D) heterogeneous integration. The backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are detailed, and 65-nm process based M3D CMOS-NEM RL circuits are proposed. It is predicted that these proposed circuits will exhibit significantly higher chip density, operation frequency, and lower power consumption compared to CMOS-only circuits in tile-to-tile operation.
research on NEM devices for logic and memory applications has been reviewed from the perspective of monolithic 3D (M3D) heterogeneous integration. In addition, the backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are described in detail. Moreover, 65-nm process based M3D CMOS-NEM RL circuits were proposed. It is predicted that proposed M3D CMOS-NEM RL circuits will exhibit 4.6x higher chip density, 2.3x higher operation frequency and 9.3x lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.
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