Journal
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Volume 69, Issue 8, Pages 7629-7638Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIE.2021.3105976
Keywords
Topology; Power conversion; Silicon carbide; Stress; Inductors; Equivalent circuits; Power harmonic filters; Current sharing; high-power applications; multilevel systems; parallel interleaved converters; silicon carbide (SiC) semiconductors
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This study investigates the generalized cascaded full-bridge concept, which aims to reduce stress on semiconductors and provide flexible design options. The structures introduced have the potential to improve performance in high-power applications by reducing losses in power semiconductors and the number of devices required.
This work investigates a generalized cascaded full-bridge (GCF) concept, which uses a full-bridge converter as a basic submodule, combined with the interleaving and cascading techniques. When compared with the traditional cascaded full-bridge (CFB) converter, the GCF topologies present the advantages of reduced current and voltage stresses on the semiconductors, and flexible design. Thereby, the resulting structures become an alternative solution for high-power applications involving high current and high voltage levels. The generalized analysis involving design guidelines for the synthesis of each topology, the system model, and possible modulation strategies are described in detail. A comparative study with the CFB-based topologies shows that the introduced structures are capable of achieving improved performance in terms of reduced losses in the power semiconductors and lower device count. A small-scale laboratory prototype of a static synchronous compensator rated at 2.2 kVA/311 V is implemented to validate the design assumptions considering the steady-state and transient performances.
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