Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 69, Issue 8, Pages 3272-3283Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2022.3168286
Keywords
Clocks; Arithmetic; Hardware; Delta-sigma modulation; Artificial neural networks; Logic gates; Generators; Stochastic computing; divider; Delta Sigma modulator; neural network
Categories
Funding
- U.S. Department of Defense [W52P1J2093009]
- NSF [CCF-1812495, 1953980, CCF-1953961, 1812467]
- Spanish Agecia Estatal de Investigation [PID2019-104207RB-I00, TSI-063000-2021127]
- Madrid Community Research Project [TAPIR-CM P2018/TCS-4496]
- Division of Computing and Communication Foundations
- Direct For Computer & Info Scie & Enginr [1953980] Funding Source: National Science Foundation
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A Delta Sigma Modulator (DSM) based stochastic divider is proposed in this paper, which offers the best computation latency and accuracy. The proposed design shows advantages in SC-based neural networks and the application to Sobol-based sequences.
The divider is one of the most complex hardware units in Stochastic Computing (SC); even though several new designs have been presented to reduce the computation latency of the conventional divider, all of them still require a considerable number of clock cycles. Moreover, they incur in low performance due to the employed arithmetic computational scheme. In this paper, a Delta Sigma Modulator (DSM) based stochastic divider is proposed. As an entirely digital circuit, the proposed divider offers the best computation latency and accuracy over all existing stochastic dividers found in the technical literature (with a typical reduction between 66.8% and 96.9% in the number of clock cycles and a reduction from 10 $<^>{{-3.4}}$ to 10 $<^>{{-3.9}}$ in the average mean square error for a 10-bit resolution). An SC-based Neural Network (NN) is considered as an initial case study to evaluate the advantages of the proposed design in an emerging application; results show that the proposed divider enables an SC-based NN to achieve a higher classification accuracy and hardware efficiency than existing designs. To show the flexibility of the proposed divider design, its application to Sobol-based sequences is also presented; also in this case, its superiority over other designs is confirmed. These features make the proposed design very attractive for hardware-constrained platforms; moreover, such a novel design approach that incorporates ideas from analog/mixed signal circuit design into a digital circuit design, can motivate other researchers to design efficient SC designs using similar schemes.
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